A typical insulated gate device (IGD) is the insulated gate transistor (IGT), a device capable of controlling a high forward current with a low bias voltage applied to its gate electrode. This gate control characteristic makes the IGT particularly useful for power control and current switching applications.
A typical IGT comprises a plurality of small, parallel-connected cells fabricated in a semiconductor substrate or wafer. Each cell comprises, in series, adjacent collector, drift, base and emitter regions of alternate conductivity types. A gate electrode is insulatively spaced from the semiconductor substrate by an insulating region which includes a plurality of contact windows, each contact window overlying one of the cells and exposing adjacent emitter and base region surfaces. Emitter and collector electrodes are connected, respectively, at opposite ends of each cell, and conduct the forward current into and out of the cell, the magnitude of the forward current being controlled by the magnitude of a bias voltage applied to the gate electrode. A typical collector electrode comprises a conductive layer in continuous ohmic contact with a single, distributed collector region shared by the plurality o cells in the wafer. In contrast, a typical emitter electrode comprises a conductive layer which makes ohmic contact with each cell at the emitter and base region surfaces exposed within each contact window.
As is known to those skilled in the art, the emitter, base and drift regions of the typical IGT cell form a first, inherent bipolar transistor, while the base, drift and collector regions form a second, inherent bipolar transistor. These first and second inherent bipolar transistors have respective forward current gains of .alpha.1 and .alpha.2, and by the nature of their construction are regeneratively coupled to form a parasitic thyristor which is susceptible to latching when the sum of these forward current gains equals or exceeds unity (i.e. .alpha.1+.alpha.2.gtoreq.1). When the parasitic thyristor in any one of the plurality of cells latches, the IGT loses gate control of the forward current, and can only be turned off through an external action such as commutation.
As is further known to those skilled in the art, one cause of parasitic thyristor latching within a cell is a reverse current flow of carriers of the base region majority concentration type from the drift region to the emitter electrode through the base region and along the emitter-base junction of the first inherent bipolar transistor. This reverse current, for example, comprises hole current carriers in an IGT having a P-conductivity type base region. This reverse current flow produces a voltage drop along the emitter-base junction which, when it exceeds a threshold voltage, forward biases this junction, thereby causing the forward current gain of the first bipolar transistor to substantially increase. Consequently, the likelihood of the forward current gains of the first and second inherent bipolar transistors exceeding unity increases substantially, as does the accompanying latching of the parasitic thyristor described above.
The voltage drop developed along the emitter-base junction of a cell can, for analytical purposes, be expressed as the product of the parasitic current flow and the resistance of the base region adjacent this junction, this base region resistance commonly being referred to as the "well resistance". While the magnitude of the reverse current varies proportionately with the magnitude of the forward, main device current during a forward conducting mode of device operation, it typically exhibits a substantially large increase during device turnoff. The metallic emitter electrode, by contacting the semiconductor base region surface exposed within the contact window, reduces the well resistance of the cell, thereby increasing the magnitude of the reverse current flow and hence the magnitude of the forward, main device current which the IGT can turn off without causing the inherent thyristor to latch.
Prior art devices are typically constructed having a plurality of small, square or circular contact windows, each of which exposes a similarly sized and shaped cell having a cell emitter region disposed continuously along its window periphery. It has been discovered that these small contact windows limit the contact area between the emitter electrode and the exposed base region surface of the cell, thereby limiting the decrease in the well resistance effected by the contact between the metal emitter electrode and the exposed surface of the semiconductor base region. Further, the limited emitter electrode-base region contact area creates a high density of reverse current flowing through the base region. This is found to be particularly so in the case of a square contact window configuration, as the flow of reverse current tends to crowd the corners of the emitter-base junction. The combined effects of the still relatively high well resistance and the high reverse current density act to increase the voltage drop along the emitter-base junctions for a given magnitude of reverse current. Since the magnitude of reverse current is a function of the forward current, the IGT becomes unduly limited in the magnitude of forward current it can reliably gate control and interrupt during turn off.
One known method of decreasing the well resistance of the cells in an IGT is to deposit a high concentration of majority carriers deeply into the base region of each cell under its emitter-base junction. This deposition creates a low-resistance path for the reverse current flow. However, this deposition requires a substantial number of additional process steps and does not produce a sufficiently large decrease in the well resistance to significantly improve the IGT operating characteristics. Further, it does not reduce the problem of reverse current crowding adjacent the emitter-base junction.